| Project Class: |
Fully digital IC |
| Technical Aspects: |
16k gates complexity, 10,7 MHz operating frequency |
| Timeframe: |
1999 - 2000 |
| Development: |
Mentor Graphics EDA tools, modified ACDPLL IP Core used |
| Prototyping: |
XILINX FPGA Spartan XCS40 in PQFP208 package,
a simple FPGA board for design provement in real customer’s system operation |
| Production: |
FPGA to ASIC conversion, ORBIT 0,5µm CMOS gate array technology, PLCC44 and MQFP44 packages |
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| Detailed Information: |
The circuit adapts a synchronous/asynchronous serial terminal to a synchronous serial network known as PCM or B-channel in the ISDN terminology. The design has more clock domains with no fixed relations and therefore the internal digital phase locked loop is used to correct clock differences. For this purpose previously developed ASICentrum ACDPLL IP macro was utilized and integrated into the design. It represents fully digital design with no external components. Usage of this IP macro caused very important short cut of the development phase.
The main circuit function is to perform some physical and link layer functions well known in the ISDN. It is a bit stuffing method to compensate asynchronous terminal bit rate with internal bit rate, a data frame composition/decomposition and a time division multiplex. The circuit works in full duplex mode and provides power-down mode to reduce power consumption while the terminal is not active. The circuit finction is controlled and monitored by the host system through host interface.
FPGA Advantage (HDL Designer Series, ModelSim, Leonardo Spectrum) - a Mentor Graphics EDA developments tools and Orbit gate array libraries were used for the design.
All design functions and modes were verified by means of the XILINX FPGA Spartan XCS40 (80% utilization) and simple FPGA board in real customer’s system operation. This way of verification enabling access to internal signals was easy and flexible both for the customer and the designer and it represents the best way how to maintain first path success in the production phase. Being provided with very good support from the customer we have delivered FPGA samples after 6 months from the beginning of the design.
An Orbit 0,5 µm CMOS gate array technology was chosen for processing of the chip in the production phase. Operating frequency of the MSBF029 is 10,7 MHz, supply voltage 3,3-5V, supply current 17mA@5V/10MHz and chip area containing 16000 logic gates measures approximately 8 sqmm. |
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| Picture 1: |
Packages for production |
| Picture 2: |
Layout |
| Picture 3: |
Prototyping board |
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Picture 1
Picture 2
Picture 3
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