| Project Class: |
DSP digital IC |
| Technical Aspects: |
RAM+ROM on chip, 22k gates complexity, 18 MHz system frequency |
| Timeframe: |
1998 - 2000 |
| Development: |
Mentor Graphics EDA tools, modified ACIIR IP Core used |
| Prototyping: |
XILINX FPGA XC4028XL in PQFP160 package + serial memory XC1701 |
| Production: |
FPGA to ASIC conversion, ORBIT 0,5µm CMOS gate array technology, PLCC44 package |
| |
|
 |
|
| Detailed Information: |
The circuit MSBF025 provides receiving and transmitting of signalling tones according customer needs. It includes the interface for the ETC5057 codec, block for the postprocessing of received tones and the host controlling microprocessor.
All design functions and modes were verified by means of the XILINX FPGA XC4028XL and simple board of the same size as the final version with two MSBF025 circuits in PLCC44 packages. Thus approx 30% of board area was saved.
For FPGA to ASIC conversion process Orbit 0,5 ūm CMOS gate array technology was chosen for the chip production phase. Operating frequency is 18 MHz (external oscillator), supply voltage +5V, chip area approximately 4,3 sqmm.
Due to our experience in telecom, DSP and filtering we were able to conclude design phase and to deliver FPGA samples after 3 months. Four designers activity, usage of our modified IP core and excellent support from the customer speeded up the design too. |
| |
| Picture 1: |
Prototyping and production boards |
| Picture 2: |
Comparison of prototyping and production packages |
|
Picture 1
Picture 2
|
