DESIGN FOR TESTABILITY

Experience in design for testability :

• test logic insertion - test points for observation
• control test points
• scan insertion
• LBIST insertion
• test coverage measuring with reserved test vectors
• automatic test pattern generation (ATPG) for general digital designs
• automatic test pattern generation for digital designs with inserted scans

The biggest realized project:

Following methods are used in ASICentrum for increasing of ICs testability during design process:

	ad-hoc methods increasing the testability without using structural methods structural methods structural design transfering the circuit or its part into a regular easy testable structure Built-in self test circuit modifications enabling the circuit to test itself Boundary Scan increases the testability of PCBs with components

Design and realization flow

1. TESTABILITY ANALYSIS

2. IMPLEMENTATION OF CHOOSEN METHODOLOGY

• "ad-hoc", scan, test points, BIST
• mostly combination of several different methods at the same time

3. NON SCAN DESIGN

• test coverage measuring based on test vectors from simulations (see digital design)
• increase of the test coverage by ATPG application

4. SCAN DESIGN

• automatic test pattern generation (ATPG)
• compresion of acquired test vectors

5. CHOICE OF OPTIMAL TEST VECTORS SET

6. DFT DOCUMENTATION CREATION

Following tools are used: 

HW - KAT7000 tester

• analog/digital
• 32 channels, extendable to 128 channels
• 10 MHz test clock
• 64k memory for test vectors
• GPIB, RS232
• possibility to connect wafer prober or handler

SW - Mentor Graphics EDA tools

• DFTAdvisor design testability analysis, test points and scan insertion
• FlexTest test coverage measuring and ATPG for digital designs (with/without scan)

SW - supportive ASICentrum tools

• SETCOVER - the choice of optimal test vectors set
• converters of test vectors formats, statistics, etc.